File name
The PCB must be in the default directory as produced by EasyEDA. The file name must start with the PCB identifier followed by an underscore and end with the version number (e.g. PCB002_JMCPU Instruction Decoder v1.0).
Units set to mil
The whole project uses mil as length units.
Design rules check
- Track width: 6
- Clearance: 6
- Via Diameter: 24
- Via Drill Diameter: 12
- Track length: (empty)
DRC must return zero defect.
Components and nets must return correct values.
Schematic synced
The Update PCB button in the schematic must update this schematic and display no pending change.
Before clicking Update PCB, the whole schematic validation checklist must have been applied, including components updated from library.
All components updated
Design/Update Components from Library must return an empty list. If it doesn't, the schematic checklist must be redone.
Routing design recommendations
The following design guidelines should be applied when routing:
- All signal traces: 6 mil wide
- Power traces for a single chip or aligned chips: 15 mil wide
- Power rails: 25mil wide
- Horizontal traces on top layer, vertical traces on bottom layer
- DIP chip pads: 45 / 27.560 mil
- Dupont pads: 62 / 35 mil
- ZIF pads: 52 / 35 mil
- All chips have an integrated 0805 decoupling capacitor to their footprint
- Resistors, capacitors and chips must have their value on the silk layer
- Align on 12.5 mil grid size for thin traces
Board layout
Backplane connectors must be at the bottom, horizontal.
Holes must be placed on the standard grid. As many holes as possible should be placed. The board can be made slightly bigger to add one more hole row if necessary. Holes must be placed on the bottom layer to see them better.
The bottom row of holes around backplane connectors is mandatory, even if the connector is omitted.
DIL chips should be placed vertically, unless the board is made significantly smaller by placing them horizontally. Chips should be placed with the notch at the top or on the left.
Chips must be all in the same direction to avoid confusion and ease reading. SMD resistors can be reversed during soldering.
Pads must be aligned on the grid. Check for small misalignments that tend to appear in EasyEDA.
Board size
The board outline must be 137.5 mil outside of the screw hole center.
Text size and orientation
Text should use one of the following font sizes:
- 8/50 mil (board description, DIL chip names)
- 6/45 mil (DIL chip names)
- 6/30 mil (DIL chip names, SMD parts)
- 5/20 mil (between SMD pads, not recommended)
Prefer horizontal text. Labels should be on top of DIP chips (notch side).
Routing optimization pass
Avoid premature optimization !
Once routing is finished, remove useless complexity in routing. Make traces as short as possible. Remove useless vias.
