JMCPU - Schematic validation process

Validation steps details

Project name and folder

The project must be in the JMCPU folder. Its name must be prefixed by JMCPU and suffixed by the version.

The project URL must match the project name using the default rules of EasyEDA.

Matches main schematic

The content must functionally match what is in the "Simple CPU" schematic.

Component names and net labels must match as closely as possible. Some minor variations are allowed, such as resistor or capacitor numbers.

Components that appear multiple times in the main schematic but only once in the PCB schematic must be renamed by removing its L/M/H suffix.

Renamed ADDL1 to ADD1

Component labels

Component labels must be customized and prefixed by their functions as much as possible, except resistors and capacitors. A minimum amount of underscores should be used.

Components must be numbered only if it makes sense to have multiple components in the same functional block. For example, while you may have MC1, MC2 and MC3 (these 3 chips are related), but ADDIA_ZERO mustn't be suffixed by a number

Components must use L/M/H suffixes to differenciate bytes inside a word. Nibbles inside a byte can use number suffixes.

Components named ADDL1, ADDL2, ADDM1, ADDM2

Component names and prefixes must be in the default position, unless the layout cannot be changed without compromising legibility drastically.

The component name must match the default name of the library. Unreadable or undesirable names can be hidden (especially default names from the EELib components that are too long or too cryptic).

Net labels and wires

Net labels must use the default position, default font and default style.

All labels must be horizontal. Labels for top pins must be horizontally aligned on the rightmost pin, stacked on top of each other.

Horizontal net labels for vertical component pins.

Net names can use underscore to separate words.

Numeric prefixes start at 0 for bit numbers, 1 otherwise.

VCC and GND labels must be used for constant logic high and low. Do not use power symbols.

Using net labels for logic constants.

Prefer net labels over messes of wire. Do not use busses.

Comparing wire mess with clean labels.

Use 10 units to space wires.

Wire spacing of 5 is too small.

All components updated

All components must be updated from the library. Saving and running Design/Update Components from Library... must show an empty list.

Components and nets check

Components and Nets in the design manager must show a complete list. All nets must be complete.

Design manager: Components (22), Nets (53/90): WRONG

Symbol design

Check that all symbols used come from the correct library.

Check that symbol styling match the whole project.

JMC logo and QR code

This logo should be removed or replaced if the PCB is modified by somebody else than the original author. It is not mandatory. The logo is protected by the same CC BY-SA license as the rest (see License on the main page). The following section should be ignored for any 3rd party modification.

All projects must contain the JMC_LOGO and JMCPU_QR components in the bottom right-hand corner.

Display name, Display prefix and Add into BOM properties must be set to No

Screw holes

Screw holes must be present on the schematic in order to ease synchronization with the PCB. The Screw hole M3 component must be used.

Display name, Display prefix and Add into BOM properties must be set to No

Main decoupling capacitor

All projects must include a 100µF 1206 decoupling capacitor named C1 connected to VCC and GND.

2 GND connectors

All PCBs must contain 2 GND connectors named GND1 and GND2 made with a 3x1 male header with all 3 pins connected to the GND net. During fabrication a thick wire will be soldered in a loop to allow connecting alligator clips easily.

Wire loop between pins 1 and 3

Very small PCBs may have only a single GND connector. Backplane or other PCBs with no GND net can skipped this entirely.

Headers match backplane reference

The project named JMCPU backplane reference contains the most up to date reference for the backplane connectors. All pins must match this reference, all net names must be exactly the same.

Unused pins must be marked as unused using the No Connect Flag (×) symbol.

Sheet info

The content must not go beyond sheet borders.

All sheets must have complete sheet info.

Sheet info and logo + QR must be locked.

Example sheet info

Simulator updated

The simulator must match the content of the schematic. All components and all nets must be exactly the same.